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Espressif Systems /ESP32-C3 /SPI0 /CTRL2

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Interpret as CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CS_SETUP_TIME 0CS_HOLD_TIME 0CS_HOLD_DELAY 0 (SYNC_RESET)SYNC_RESET

Description

SPI0 control2 register.

Fields

CS_SETUP_TIME

(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
CS_HOLD_TIME

Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
CS_HOLD_DELAY

These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
SYNC_RESET

The FSM will be reset.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data